This invention relates to logic circuit using registers and to output circuits for programmable logic Q array (PLA) circuits. PLA circuits are well known in the art. A description of PLA circuits can be found in PAL Programmable Array Logic Handbook published by Monolithic Memories, Inc., the assignee of this application. PAL is a registered trademark of Monolithic Memories, Inc., the assignee of this application. FIG. 1 illustrates a simple PLA circuit 10. Included in circuit 10 are four input terminals I0, I1, I2, and I3. Each input terminal I0 through I3 is coupled to the input lead of a buffer B0 through B3. Each buffer has an inverting output lead and a noninverting output lead. For example buffer B0 has an output lead 12a which provides a signal ISO, which is the inverse of the signal present on terminal I0. Similarly, buffer B0 has an output lead 12b, which provides a signal IS0, which is equal to the signal present at terminal I0. Each of the output signals from buffers B0 to B3 are presented as an input signal to an AND gate 14a. AND gate 14a is an 8 input AND gate, and each of the output leads of buffers B0 to B3 is uniquely coupled to a single input lead of AND gate 14a. Thus, FIG. 2a illustrates the eight input leads to AND gate 14a. FIG. 2b illustrates AND gate 14a using the more conventional notation. In addition, fifteen other AND gates, 14b to 14p are also provided and are connected to the output leads of buffer B0 through B3 in the same manner as AND gate 14a. Thus, each of AND gates 14a-14p is coupled to all eight output leads of buffers B0 to B3. However, a purchaser of a PLA circuit has the option of severing the connection between a given buffer output lead and a given AND gate 14a to 14p. This is done by opening a fuse similar to the fuses employed in programmable read only memories. In this way, the user can cause each AND gate 14a through 14p to provide a unique output signal dependent on a particular set of input signals.
Also as can be seen in FIG. 1, a first OR gate 16a includes four input leads coupled to AND gates 14m, 14n, 14o, and 14p.OR gate 16a generates an output signal on an output lead O.sub.0 therefrom. Similarly, an OR gate 16b receives output signals from AND gates 14i, 14j, 14k and 14l and generates an output signal on a lead O.sub.1 therefrom. The output signals from OR gate 16c and 16d are similarly derived from the remaining AND gates. (Unlike the input leads of AND gates 14a to 14p, the input leads of OR gates 16a to 16d are fixed, i.e., they cannot be programmed by opening fuses.) In this way, a programmable logic circuit 10 is provided which provides arbitrary programmable Boolean functions which can be used in a variety of applications. A programmable logic circuit which provides "arbitrary programmable Boolean functions" is one which can be programmed by the system designer to provide any of a number of Boolean functions required in a given system design. This semicustom circuit provides an inexpensive replacement for a large number of TTL circuits which would otherwise be required. As is also known in the art, different numbers of input terminals and different numbers of output terminals are provided by different generic types of PLA circuits such as model number PAL 10A8 and model number PAL 12H6, both manufactured by Monolithic Memories, Inc.
It is also known in the art to provide a logic array in which the input leads to the OR gates are programmable. For example, it is known to provide an array such as the one in FIG. 1, except that the output lead from each AND gate 14a through 14p is programmably connected to OR gates 16a through 16d. The term "PLA" in this patent includes devices having OR gates with fixed inputs and programmable inputs.
An improvement of the circuit of FIG. 1 is illustrated in the prior art circuit of FIG. 3. In FIG. 3, each of the output leads of OR gates 16a through 16d is coupled to a circuit such as circuit 18 of FIG. 3. FIG. 3 illustrates the output circuit coupled to output lead O.sub.0. However, it is understood that all of the output leads O.sub.0 through O.sub.3 are coupled to identical circuits. Output lead O.sub.0 is coupled to a D flip flop 20 and a first input lead 26 of a multiplexer 28. The Q output lead 22 of flip flop 20 is connected to a second input lead 30 of multiplexer 28. An output lead 32 of multiplexer 28 is coupled to the input lead of an inverting three-state buffer 36. As is well known in the art, a three-state buffer is a buffer which can drive an input lead with a logical high signal or drive the output lead with a logical low signal or go into a high impedence mode whereby the tri-state buffer is not driving the output lead at all. The clock input lead 24 of flip flop 20 is controlled by a clock line CLK which also provides the clock input signals for the D flip flops that are coupled to output leads O.sub.1 to O.sub.3 (not shown). The CLK line is driven by a dedicated pin on the PLA integrated circuit. The select control for multiplexer 28 is controlled by a select line B which also controls the state of multiplexers coupled to output leads O.sub.1 through O.sub.3 (not shown) Finally, an output enable line OE (driven by a dedicated pin on the PLA integrated circuit or from combinatorial logic within the array) determines when output buffer 36 goes into the high impedance mode. Output line OE also controls the other output buffers coupled to output leads O.sub.1 to O.sub.3 (not shown).
In operation, clock line CLK causes the information on output lead O.sub.0 to be stored in flip flop 20. Select line B determines whether the information on output lead O.sub.0 or the information stored in flip flop 20 will be presented to buffer 36. The state of select line B is determined by a select fuse (not shown) located within the integrated circuit. Thus, the user programming PLA 10 determines whether the signal on output lead O.sub.0 is presented to buffer 36 or whether the data stored in flip flop 20 is presented to buffer 36. Since this selection is made by blowing a fuse, it is irreversible. The g configuration of FIG. 3 has several other disadvantages. For example, each output circuit 18 cannot be individually configured in the registered or combinatorial mode, i.e., once select line B is set, it is set for all the output circuits coupled to output leads O.sub.0 through O.sub.3.